1. Field of the Invention
The present invention relates to a semiconductor chip package structure and a method for manufacturing the same, and more particularly to a multichip stacking package structure and a method for manufacturing the same.
2. Description of Related Art
A multichip package (MCP) structure is a package with a plurality of semiconductor chips integrated into a single package structure, so that density of electronic components is enhanced to shorten the electrical connecting paths between electronic components. This package not only reduces the overall size of the multichip but also enhances overall performance.
In conventional multichip package structure, a plurality of chips are stacked vertically, alternately, stepwise or otherwise, and then each of the chips is electrically connected to a substrate through wire bonding. In multi-semiconductor chips stacking package technology, a stacking package technology of multichip with same size is a conventional package technology.
In the known technology, please refer to FIG. 1, FIG. 1 is a sectional schematic diagram of a conventional stacking multichip package structure; wherein a lower surface of a first chip 13 is stacked on a substrate 11, and a lower surface of a second chip 14 is stacked on an upper surface of the first chip 13 by a interlaced reciprocation stacking way; further, a lower surface of a third chip 15 is stacked on the second chip 14 by the interlaced reciprocation stacking way, and a lower surface of a fourth chip 16 is stacked on the upper surface of the third surface by the interlaced reciprocation stacking way. Besides, chip pads on the upper surfaces of each chip are respectively electrically connected to a plurality of electrical connecting pads 12 on the substrate 10 by a plurality of wires. Moreover, these chips are bonded to each other by a die adhesion layer 17. An empty space is formed under the bond pad of the third chip 15; therefore, a support is not enough during wire bonding, so that a problem of chip cracks is generated. Hence, in order to satisfy a stress during wire bonding, a thickness of the third chip 15 should be thickened to avoid damages of chips.
Besides, in the other known technology, such as Taiwan Patent Publication No. 201222737A1, a semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.
However, as shown in FIG. 1, the stacking multichip package structure 1 should increase the thickness of chips to avoid damages of chips. But, the complexity for preparing materials is increased during increasing the thickness of the chips; therefore, a problem for controlling the thickness of chip to be not easy is generated. Besides, in the other known technology, chips are electrically connected to the substrate by wire bonding, but the chips are cracked easily through wire bonding. Therefore, there is an urgent need for a multichip stacking package structure and a method for manufacturing the same, which provides an optimum support by changing a position of wire bonding, and provides a spacer without wire bonding on it to avoid the chip crack. Further, the present invention provides chips with the same thickness to simplify process of production and control the cost of production.